TEACHING IN THE CLOUD MICROELECTRONICS UBIQUITOUS LAB (MULAB)

CAD laboratory students activity is mandatory for microelectronics teaching. This, applied in the deep-submicron era, creates new challenges to couple software management simplicity to user friendliness inside lab sessions, which requires the use of complex tools and concepts. In this paper, a new approach to microelectronics CAD deployment is presented, based on virtualization capabilities of new servers hardware and software technology. A test case, realized at Politecnico di Torino, degree of Electronic Engineering, is presented, with real world results on resource consumption and user satisfactio

vrLab: A Virtual and Remote Low Cost Electronics Lab Platform

SARS-CoV2 pandemic stressed the need to increase adoption of remote teaching. Technical courses, specifically electronic engineering ones, suffered the miss of real lab experiments directly carried out by students. In this paper a new approach is presented, based on the usage of very low cost experimental boards, which act both as a measurement instrument and a programmable prototype circuit. A first board, targeted to analog and digital electronics courses experiments, has been designed, and is described in this paper

Exploiting generalized de-Bruijn/Kautz topologies for flexible iterative channel code decoder architectures

Modern iterative channel code decoder architectures have tight constrains on the throughput but require flexibility to support different modes and standards. Unfortunately, flexibility often comes at the expense of increasing the number of clock cycles required to complete the decoding of a data-frame, thus reducing the sustained throughput. The Network- on-Chip (NoC) paradigm is an interesting option to achieve flexibility, but several design choices, including the topology and the routing algorithm, can affect the decoder throughput. In this work logarithmic diameter topologies, in particular generalized de-Bruijn and Kautz topologies, are addressed as possible solutions to achieve both flexible and high throughput architectures for iterative channel code decoding. In particular, this work shows that the optimal shortest-path routing algorithm for these topologies, that is still available in the open literature, can be efficiently implemented resorting to a very simple circuit. Experimental results show that the proposed architecture features a reduction of about 14% and 10% for area and power consumption respectively, with respect to a previous shortest-path routing-table-based design

Feedbacks in QCA: a Quantitative Approach

In the post-CMOS scenario a primary role is played by the quantum-dot cellular automata (QCA) technology. Irrespective of the specific implementation principle (e.g., either molecular, or magnetic or semiconductive in the current scenario) the intrinsic deep-level pipelined behavior is the dominant issue. It has important consequences on circuit design and performance, especially in the presence of feedbacks in sequential circuits. Though partially already addressed in literature, these consequences still must be fully understood and solutions thoroughly approached to allow this technology any further advancement. This paper conducts an exhaustive analysis of the effects and the consequences derived by the presence of loops in QCA circuits. For each problem arisen, a solution is presented. The analysis is performed using as a test architecture, a complex systolic array circuit for biosequences analysis (Smith–Waterman algorithm), which represents one of the most promising application for QCA technology. The circuit is based on nanomagnetic logic as QCA implementation, is designed down to the layout level considering technological constraints and experimentally validated structures, counts up to approximately 2.3 milion nanomagnets, and is described and simulated with HDL language using as a testbench realistic protein alignment sequences. The results here presented constitute a fundamental advancement in the emerging technologies field since: 1) they are based on a quantitative approach relying on a realistic and complex circuit involving a large variety of QCA blocks; 2) they strictly are reckoned starting from current technological limits without relying on unrealistic assumptions; 3) they provide general rules to design complex sequential circuits with intrinsically pipelined technologies, like QCA; and 4) they prove with a real application benchmark how to maximize the circuits performance

Biosequences analysis on NanoMagnet Logic

In the last decade Quantum dot Cellular Automata technology has been one of the most studied among the emerging technologies. The magnetic implementation, NanoMagnet Logic (NML), is particularly interesting as an alternative solutions to CMOS technology. The main advantages of NML circuits resides in the possibility to mix logic and memory in the same device, the expected low power consumption and the remarkable tolerance to heat and radiations. NML and QCA circuits behavior is different w.r.t. their CMOS counterparts. Consequently architecture organization must be tailored to their characteristics, and it is important to identify which applications are best suited for this technology. Our contribution reported in this paper represents a considerable step-forward in this direction. We present an optimized implementation on NML technology of an hardware accelerator for biosequences analysis. The architecture leverages the systolic array structure, which is the best organization for this technology due to the regularity of the layout. The circuit is described using a VHDL model, simulated to verify the correct functionality from the application point of view, and performance are evaluated, both in terms of speed and power consumption. Results pinpoints that NML technology with the appropriate clock solution can reach a considerable reduction in power consumption over CMOS. This analysis highlights quantitatively, and not only qualitatively, that NML logic is perfectly suited for Massively Parallel Data Analysis applications

MEDEA: A Hybrid Shared-memory/Message-passing Multiprocessor NoC-based Architecture

The shared-memory model has been adopted, both for data exchange as well as synchronization using semaphores in almost every on-chip multiprocessor implementation, ranging from general purpose chip multiprocessors (CMPs) to domain specific multi-core graphics processing units (GPUs). Low-latency synchronization is desirable but is hard to achieve in practice due to the memory hierarchy. On the contrary, an explicit exchange of synchronization tokens among the processing elements through dedicated on-chip links would be beneficial for the overall system performance. In this paper we propose the Medea NoC-based framework, a hybrid shared-memory/message-passing approach. Medea has been modeled with a fast, cycle-accurate SystemC implementation enabling a fast system exploration varying several parameters like number and types of cores, cache size and policy and NoC features. In addition, every SystemC block has its RTL counterpart for physical implementation on FPGAs and ASICs. A parallel version of the Jacobi algorithm has been used as a test application to validate the metodology. Results confirm expectations about performance and effectiveness of system exploration and design

Ta/CoFeB/MgO analysis for low power nanomagnetic devices

The requirement of high memory bandwidth for next-generation computing systems moved the attention to the development of devices that can combine storage and logic capabilities. Domain wall-based spintronic devices intrinsically combine both these requirements making them suitable both for non-volatile storage and computation. CoPt and CoNi were the technology drivers of perpendicular Nano Magnetic Logic devices (pNML), but for power constraints and depinning fields, novel CoFeBMgO layers appear more promis- ing. In this paper, we investigate the Ta2CoFeB1MgO2Ta3 stack at the simulation and experimental level, to show its potential for the next generation of magnetic logic devices. The micromagnetic simulations are used to support the experiments. We focus, first, at the experimental level measuring the switching field distribution of patterned magnetic islands, Ms via VSM and the domain wall speed on magnetic nanowires. Then, at the simulation level, we focus on the magnetostatic analysis of magnetic islands quantifying the stray field that can be achieved with different layout topologies. Our results show that the achieved coupling is strong enough to realize logic computation with magnetic islands, moving a step forward in the direction of low power perpendicularly magnetized logic devices

Design of Pyrrole-Based Gate-Controlled Molecular Junctions Optimized for Single-Molecule Aflatoxin B1 Detection

Food contamination by aflatoxins is an urgent global issue due to its high level of toxicity and the difficulties in limiting the diffusion. Unfortunately, current detection techniques, which mainly use biosensing, prevent the pervasive monitoring of aflatoxins throughout the agri-food chain. In this work, we investigate, through ab initio atomistic calculations, a pyrrole-based Molecular Field Effect Transistor (MolFET) as a single-molecule sensor for the amperometric detection of aflatoxins. In particular, we theoretically explain the gate-tuned current modulation from a chemical–physical perspective, and we support our insights through simulations. In addition, this work demonstrates that, for the case under consideration, the use of a suitable gate voltage permits a considerable enhancement in the sensor performance. The gating effect raises the current modulation due to aflatoxin from 100% to more than 103÷104 %. In particular, the current is diminished by two orders of magnitude from the μA range to the nA range due to the presence of aflatoxin B1. Our work motivates future research efforts in miniaturized FET electrical detection for future pervasive electrical measurement of aflatoxins

Charge injection E/D MESFET structures for high speed and low power applications

In this paper new dynamic charge injection E/D logics are presented and compared with traditional dynamic ones such as TDFL (Two Phase Dynamic Fet Logic). The main drawbacks of TDFL will be analyzed together with the advantages offered with respect to the static DCFL based topologies; a tentative structure has been derived (MTDFL - Modified TDFL) to comply with the VLSI requirements; then the advantages of the charge injection principles applied to the design of new logic topologies are inspected and used in a pseudo complementary structure (PCDL - Pseudo Complementary Dynamic Logic). The results of the simulations for these structures are presented together with the design of a 4-bits pipelined adder simulated at 2 GHz with a power dissipation 20 times lower than a DCFL implementation